# Source
source ~cvsd/cvsd.cshrc 合成軟體使用的LICENCE
source ~cvsd/verdi.cshrc 波形軟體使用的LICENCE
(01) Compiler 編譯程式
[檔案] testbench與design的verilog檔案
[內容]
若要產生波形檔,須在testbench內的Initial block加入,
$dumpfile(“WAVE.fsdb”);
$dumpvars;
gate-level simulation則要使用
ncverilog +access+r test_alu.v alu_s.v tsmc18.v
檢查time violation的方式,在testbench上加入此行,瞭解delay的情況。
$sdf_annotate(“alu_s.sdf”,my_alu);
[指令] 使用MIPS_test.v測試MIPS.v檔案
ncverilog +access+r MIPS_test.v MIPS.v
(02) Debugging 除錯
nWave &
File→Open→載入FSDB檔案→看波形
看波形Debug真的比較方便,我之前都傻傻的用輸出指令慢慢對變數內容。Orz|||
(03) Memory Generator 產生記憶體
Run the memory compiler,這是一個會認機器的指令,最好使用TAB鍵來確認路徑。
/home/raid1_1/cic/CBDK018_TSMC_Artisan/CIC/Memory/ra1shd/bin/ra1shd &
從這裡面挑選主機,http://cad.ee.ntu.edu.tw/
如果出現 This program is not supported on this machine,可能是伺服器作業系統的問題。
列表中有RHEL(Red Hat)和Solaris兩種類型,選擇Solaris的主機才可以正常啟動。
Ram的命名最好與性質相關,方便以後使用,例如:HSs18n_64x8代表的是…
High Speed single port 0.18μm normal RAM with 64words/8bit.
ra1sh is used for high-speed single-port SRAM,
ra1shd is used for larger size SRAM,
ra2sh is for high-speed dual port SRAM designs.
rf2sh_64x16 = “high-speed dual port 64words/16bit “
高速雙埠同步SRAM(RA2SH)
高速雙埠同步Register File(RF2SH)
高速單埠同步SRAM(RA1SH)
高速單埠同步Register File(RF1SH)
[產生檔案]
選擇PostScript Datasheet,將會產生HSs18n_64x8.ps
選擇Verilog Model,將會產生HSs18n_64x8.v
選擇Synopsys Model,將會產生HSs18n_64x8_fast_syn.lib,HSs18n_64x8_typical_syn.lib, HSs18n_64x8_slow_syn.lib.等Liberary。
選擇“Utilities -> Write Spec”輸出SPEC。
[模擬]
ncverilog +access+r test_ram.v HSs18n_64x8.v
[設計中如何使用Memory呢?]
首先,先看spec上memory的pin腳,input與output。
[如何測試Memory呢?]
宣告─
HSs18n_64x8 my_ram(.A(Addr),
.D(I),
.CLK(~clk),
.CEN(CEB),
.WEN(WEB),
.OEN(OEB),
.Q(O) );
以.A(Addr)為例,括號內是testbench的變數宣告reg Addr[5:0],程式內以此變數做運算。
括號外為Memory的PIN腳,A[5:0]用做儲存Address,宣告的size必須相同。
(04) Synthesis 合成電路
在合成電路時,必須考慮到在設計階段的寫作習慣,避免寫出無法合成的電路。
最常見的包含Initial block與迴圈的使用,一般不建議放入設計當中。
這部份是我最常犯的錯誤,因為太過習慣C語言的思考方式,
忽略掉硬體本身的設計限制,所以容易寫出無法合成的設計。Q_____Q
[環境設定]
source /usr/spring_soft/CIC/debussy.cshrc
cp ~cvsd/CUR/Synthesis/Lab1/synopsys_dc.setup ./.synopsys_dc.setup
[準備檔案]
設計的verilog檔案,.synopsys_dc.setup,以及之前記憶體產生的Liberary
[執行指令]
dc_schell (指令介面)
dv & (GUI介面)
[合成]
讀取檔案後,開始檢查是否有產生Latch或者是正常的Flip-Flop,若產生latch則須回頭修正程式內容。
可用G-tech MAP或Symbol view的方式,檢視電路。
[Set clock] 設定clk時脈的頻率
“Attributes”-“Specify Clock”.
create_clock -name “clk” -period 10 -waveform {“0” “5”} {“clk”}
set_dont_touch_network [ find clock clk]
set_fix_hold clk
代表的意義是10ns(100MHz),Rising為0,Falling為5的clk。
並使用以下指令改變wire load
set_operating_conditions “typical” -library “typical”
set_wire_load_model -name “ForQA” -library “typical”
set_wire_load_mode “segmented”
[Set operating environment] 設定I/O pin的delay。
“Attribute”-“operating environment”-“input delay”.
set_input_delay -clock clk 2.5 inputA[*]
set_input_delay -clock clk 3.8 inputB[*]
set_input_delay -clock clk 4.5 instruction[*]
set_input_delay -clock clk 5.2 reset
set_output_delay -clock clk 8 alu_out[*]
“Attribute”-”optimization Constraints”-“Design constraints”
set_boundary_optimization “*”
set_fix_multiple_port_nets -all -buffer_constant
set_max_area 0
set_max_fanout 8 ALU 設定分支數
set_max_transition 1 ALU
[Check Design]
“Design”-”Check Design”.
如果產生了error或warning則重複之前步驟。
[Design Optimization]
“Design”-”Compile Design”.
compile -map_effort medium
[Report] 產生timing、area、power的結果
report_timing -path full -delay max -max_paths 1 -nworst 1
report_power
report_area -nosplit
“Timing”=>“Report Timing Paths”; 注意,slack值須為正。
“Design” => “Report Power”;
“Design”=>“Report Area”;
[錯誤情況] 我目前在這邊遇到問題(哭哭),希望能快點解掉。
Timing
(Path is unconstrained)
可以檢查看看是不是有與timing相關的設定沒有設定好,每一個input、output pin腳、clk的delay, 或者library是否提供正確的路徑。
Area
Net Interconnect area: undefined (Wire load has zero net area)
因為你沒設wire load model,僅此而已。所以你要在合成的時候下以下指令(或寫進你的script):
set_wire_load_model -name “umc18_wl50” -library “typical” 我想你的問題應該會得到解決。
若你還是有問題,再確保你的.synopsys_dc.setup(有.)有include “typical.db”,對照SPEC裡寫的,該include的都別少就安全了。
[存檔]
“File”-“Save”
“File”-”Save As”choose “DDC” formate
“File”-”Save As” ,choose “VERILOG” formate with the File name “ALU_syn”
“write_sdf -version 2.1 ALU.sdf”. 用來儲存the timing information。
“write_script > script_file”
“History”-”Save Contents As…”→“include script_file”
“History”-”Save Contents As…”→“File”-“Execute Script”
[Gate-level simulation]
For verilog gate-level simulation, you may add “$sdf_annotate(sdf_file,
testbench_module.ALU_instance);” in initial block in your test bench to use
timing information for simulation.
[Synopsys Memory Library Generation]
準備好那些LIBERARY檔案。
dc_shell -xg
dc_shell> read_lib NAME.lib
dc_shell> write_lib USER_LIB –output OUTPUT_FILE_NAME
舉例,
dc_shell> read_lib HSs18n_64x8_typical_syn.lib
dc_shell> write_lib HSs18n_64x8 ‐output HSs18n_64x8_typical_syn.db
The produced .db files are the synthesis models that Synospys Design Compiler can use. Remember to add where you put the .db files in the “search_path” and add the .db file names in the “link_library” and “target_library” in your .synopsys_dc.setup before further synthesis of the RAM.
(05) Desigh for Test DFT
[網路上的定義]
所謂DFT,是在IC設計中預先將一些與測試設備相對應的參數或是電路植入晶片佈局中,藉此提高IC的測試覆蓋率,如此一來不但能將複雜IC的測試難度與成本大幅降低,也能提高測試的品質、確保IC的“健康”。
[待續]
(06) ATPG
(07) STA
(08) Encounter
(09) DRC
(10) LVS
(11) Design Verification
(12) FPGA
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